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Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO ADP5022
FEATURES
Input voltage range: 2.4 V to 5.5 V Tiny 16-ball, 2 mm x 2 mm WLCSP package Overcurrent and thermal protection Soft start Factory programmable undervoltage lockout on VDDA system supply of either 2.2 V or 3.9 V Factory programmable default output voltages for all 3 channels Buck1 and Buck2 key specifications Current mode architecture for excellent transient response 3 MHz operating frequency Uses tiny multilayer inductors and capacitors Forced PWM and auto PWM/PSM modes Out-of-phase operation for reduced input filtering 100% duty cycle low dropout mode 24 A typical quiescent current per channel, no switching LDO key specifications Stable with 1 F ceramic output capacitors High PSRR 60 dB up to 10 KHz Low output noise 65 V rms output noise at VOUT3 = 3.3 V Low dropout voltage: 150 mV @ 150 mA load 11 A typical ground current at no load
GENERAL DESCRIPTION
The ADP5022 is a micro power management unit (micro PMU) that combines two high performance buck regulators and a low dropout regulator (LDO) in a tiny 16-ball 2.08 mm x 2.08 mm WLCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space required. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators automatically switch operating modes, depending on the load current level. At higher output loads, the buck regulators operate in PWM mode. When the load current falls below a predefined threshold, the regulators operate in power save mode (PSM), improving the light-load efficiency. The two bucks operate out-of-phase to reduce the input capacitor requirement and noise. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5022 LDO extends the battery life of portable devices. The LDO maintains power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator in the ADP5022 has a dedicated, independent enable pin. A high voltage level applied to the enable pin activates the respective regulator. The default output voltages are factory programmable and can be set to a wide range of options.
APPLICATIONS
USB devices Handheld products Multivoltage power for processors, ASICS, FPGAs, and RF chipsets
ADP5022
VIN = 2.4V TO 5.5V VIN1 C2 4.7F ON OFF SW1 L1 1H
COUT_3 C4 10F VOUT1 @ 600mA C3 C4
BUCK1
EN1
EN_BK1
VOUT1 PGND1 MODE PWM L2 1H
MODE VIN2 C3 4.7F OFF MODE ON EN2 VDDA C1 1F OFF VIN3 ON EN3 SW2 VOUT2 PGND2
PWM/PSM VOUT2 @ 600mA C5 10F
C1
C2
BUCK2
EN_BK2
5.0mm
INDUCTOR INDUCTOR
LDO1
EN_LDO1 AGND
VOUT3 C6 1F
VOUT3 @ 150mA
08253-001
COUT_1
COUT_2
4.7mm
Figure 1. Typical Applications Circuit
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Figure 2. Typical PCB Layout
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08253-061
L1
ADP5022 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Buck1 and Buck2 Specifications ................................................. 4 LDO Specifications ...................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Data ................................................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 16 Power Management Unit........................................................... 16 Buck Section................................................................................ 17 LDO Section ............................................................................... 18 Applications Information .............................................................. 19 Buck External Component Selection....................................... 19 LDO Capacitor Selection .......................................................... 20 PCB Layout Guidelines .................................................................. 22 Evaluation Board schematics and Artwork ................................ 23 Suggested Layout ........................................................................ 23 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
11/09--Revision A: Initial Version
Rev. A | Page 2 of 28
ADP5022 SPECIFICATIONS
VDDA = VIN1 = VIN2 = 3.6 V, VIN3 = (VOUT3 + 0.5 V) or 2.4 V, whichever is greater, VIN3 VIN1, TJ = -40C to +125C, unless otherwise noted. 1 Table 1.
Parameter INPUT VOLTAGE RANGE System and Buck Input Supplies Voltage Range Symbol VDDA, VIN1, and VIN2 VIN3 IGND-SD EN1 = EN2 = EN3 = GND EN1 = EN2 = EN3 = GND TJ = -40C to +85C TJ rising Test Conditions/Comments Low UVLO level models High UVLO level models LDO Input Supply Voltage Range SHUTDOWN CURRENT Min 2.4 4.5 2.3 0.5 2 Typ Max 5.5 5.5 5.5 Unit V V V A A
THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN1, EN2, EN3, MODE INPUTS EN1, EN2, EN3, MODE Input Logic High EN1, EN2, EN3, MODE Input Logic Low EN1, EN2, EN3, MODE Input Leakage Current STANDBY CURRENT All Channels Enabled, No Load All Channels Enabled, No Load, No Buck Switching VIN3 UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling VDDA UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling
TSDTH TSDHYS VIH VIL VI-LEAKAGE ISTBY ISTBY-NOSW UVLOVIN3RISE UVLOVIN3FALL UVLOVDDARISE UVLOVDDAFALL
150 20 1.2 0.05 80 59 0.4 1
C C V V A A A V V V V V V
VDDA = VIN1 = VIN2 VDDA = VIN1 = VIN2 Pin at (VDDA = VIN1 = VIN2) or GND
85 2.20
1.45 High UVLO level (factory programmed) Low UVLO level (factory programmed) High UVLO level (factory programmed) Low UVLO level (factory programmed) 4.15 2.35 3.40 2.00
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control.
Rev. A | Page 3 of 28
ADP5022
BUCK1 AND BUCK2 SPECIFICATIONS
VDDA = VIN1 = VIN2 = 3.6 V, VIN3 = (VOUT3 + 0.5 V) or 2.4 V, whichever is greater, VIN3 VIN1, TJ = -40C to +125C, unless otherwise noted. 1 Table 2.
Parameter OPERATING SUPPLY CURRENT Buck1 Only Buck2 Only Buck1 and Buck2 Only OUTPUT VOLTAGE ACCURACY Symbol IGND1 IGND2 IGND1-2 VOUT1, VOUT2 PWM mode, VIN1 = VIN2 = 2.4 V to 5.5 V, ILOAD1 = ILOAD2 = 0 mA - 600 mA POWER SAVE MODE TO PWM CURRENT THRESHOLD PWM TO POWER SAVE MODE CURRENT THRESHOLD SW CHARACTERISTICS, BUCK1 and BUCK2 PFET On Resistance NFET On Resistance Current Limit OSCILLATOR FREQUENCY START-UP TIME 2 From Shutdown State
1 2
Test Conditions/Comments ILOAD1 = 0 mA, device not switching, EN1 = VDDA, EN2 = EN3 = GND ILOAD2 = 0 mA, device not switching, EN2 = VDDA, EN1 = EN3 = GND ILOAD1 = ILOAD1 = 0 mA, device not switching, EN1 = EN2 = VDDA, EN3 = GND
Min
Typ 24 32 48
Max
Unit A A
64
A
-3 105 100
+3
% mA mA
IPSM-PWM IPWM-PSM
RPFET RNFET ILIMIT1, ILIMIT2 FSW TSTARTUP12-SD
Typical at VIN1 = VIN2 = 3.6 V Typical at VIN1 = VIN2 = 5.0 V Typical at VIN1 = VIN2 = 3.6 V Typical at VIN1 = VIN2 = 5.0 V PFET switch peak current limit
750 2.5
165 125 125 100 950 3.0 250
275 220 1050 3.5
m m m m mA MHz s
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. Start-up time is defined as the time from a rising edge on EN1/EN2 to VOUT1/VOUT2 reaching 90% of their nominal value.
Rev. A | Page 4 of 28
ADP5022
LDO SPECIFICATIONS
VDDA = VIN1 = VIN2 = 3.6 V, VIN3 = (VOUT3 + 0.5 V) or 2.3 V, whichever is greater, VIN3 VIN1, IOUT3 = 10 mA; CIN3 = COUT3 = 1 F, TJ = -40C to +125C, unless otherwise noted. 1 Table 3.
Parameter OPERATING SUPPLY CURRENT 2 Symbol IVIN3-GND Test Conditions/Comments IOUT3 = 0 A IOUT3 = 10 mA IOUT3 = 150 mA OUTPUT VOLTAGE ACCURACY VOUT3 100 A < IOUT3 < 150 mA, VIN3 = (VOUT3 + 0.5 V) to 5.5 V REGULATION Line Regulation Load Regulation 3 DROPOUT VOLTAGE 4 VOUT3/VIN3 VOUT3/IOUT3 VDROPOUT START-UP TIME 5 From Shutdown State CURRENT-LIMIT THRESHOLD 6 OUTPUT NOISE VIN3 = (VOUT3 + 0.5 V) to 5.5 V, IOUT = 1 mA IOUT3 = 1 mA to 150 mA VOUT3 = 3.0 V, IOUT3 = 10 mA VOUT3 = 3.0 V, IOUT3 = 150 mA -2 +2 % Min Typ 11 16 31 Max 21 29 43 Unit A A A
-0.03 0.002 7 110 200 240 65 52 40 60 66 70
+0.03 0.0075
%/ V %/mA mV mV s mA V rms V rms V rms dB dB dB
150
TSTARTUP3-SD ILIMIT3 OUTNOISE 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 10 Hz to 100 kHz, VIN3= 5 V, VOUT3 = 2.4 V 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.2 V
160
350
POWER SUPPLY REJECTION RATIO
PSRR 10 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 10 kHz, VIN3 = 5 V, VOUT3 = 2.3 V 10 kHz, VIN3 = 5 V, VOUT3 = 1.2 V
1 2
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control. LDO operating supply current is the current drawn from VIN3 to AGND when the LDO is enabled. Whenever any regulator channel is enabled, current is drawn from VIN1 to AGND. This current is 8 A typical and is included in the IGND1, IGND2, and IGND1-2 specifications. 3 Based on an end-point calculation using 1 mA and 150 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 5 Start-up time is defined as the time between the rising edge of EN3 to VOUT3 being at 90% of its nominal value. 6 Current-limit threshold is defined as the current at which VOUT3 drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.
Rev. A | Page 5 of 28
ADP5022 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter VDDA, VIN1, VIN2, VIN3, VOUT1, VOUT2, VOUT3, EN1, EN2, EN3, MODE to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.3 V to +6 V -65C to +150C -40C to +125C JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
JA of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4" x 3" circuit board. Refer to JEDEC JESD 51-9 for detailed information on the board construction. For additional information, see the AN-617 Application Note, MicroCSPTM Wafer Level Chip Scale Package.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered on a circuit board. Table 5. Thermal Resistance
Package Type 16-Ball, 0.5 mm Pitch WLCSP JA 65 Unit C/W
THERMAL DATA
Absolute maximum ratings apply individually only, not in combination. The ADP5022 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature (TA) does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature may exceed the maximum limit as long as the junction temperature is within specification limits. TJ of the device is dependent on TA, the power dissipation (PD) of the device, and the junction-to-ambient thermal resistance (JA) of the package. Maximum TJ is calculated from TA and PD using the following formula: TJ = TA + (PD x JA)
ESD CAUTION
Rev. A | Page 6 of 28
ADP5022 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1 INDICATOR 1 2 3 VIN3 4 VDDA
VOUT3 AGND A VIN1 B SW1 C EN3 EN1
EN2
VIN2
MODE
SW2
PGND1 VOUT1 VOUT2 PGND2 D TOP VIEW (BALL SIDE DOWN) Not to Scale
08253-002
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 Mnemonic VOUT3 AGND VIN3 VDDA VIN1 EN1 EN2 VIN2 SW1 EN3 MODE SW2 PGND1 VOUT1 VOUT2 PGND2 Description LDO Output Voltage and Sensing Input. Analog Ground. LDO Input Supply (VIN3 VIN1 = VIN2 = VDDA). Supply Input for the Housekeeping Block and UVLO Sensing. Buck1 Input Supply (VIN1 = VIN2 = VDDA). Buck1 Activation. Set EN1 = high: turn on Buck1. Set EN1 = low: turn off Buck1. Buck2 Activation. Set EN2 = high: turn on Buck2. Set EN2 = low: turn off Buck2. Buck2 Input Supply (VIN2 = VIN1 = VDDA). Buck1 Switching Node. LDO Activation. Set EN3 = high: turn on LDO. EN3 = low: turn off LDO. Buck1/Buck2 Operating Mode: MODE = high: forced PWM operation. MODE = low: auto PWM/PSM operation. Buck2 Switching Node. Dedicated Power Ground for Buck1. Buck1 Output Voltage Sensing Input. Buck2 Output Voltage Sensing Input. Dedicated Power Ground for Buck2.
Rev. A | Page 7 of 28
ADP5022 TYPICAL PERFORMANCE CHARACTERISTICS
VIN1 = VIN2 = VIN3 = VDDA = 5.0 V, TA = 25C, unless otherwise noted.
T
T
SW
4
VOUT1
1
2
VOUT
VOUT2
2
1
EN IIN
VOUT3
3
3
CH1 2.00V CH3 2.00V
BW BW
CH2 2.00V
BW
M 200s T 45.40%
A CH1
1.92V
CH1 2.00V CH3 5.00V
BW BW
CH2 50.0mA BW M 40.0s BW CH4 5.00V T 11.20%
A CH3
2.2V
Figure 4. 3-Channel Start-Up Waveforms, VIN3 Cascaded from VOUT1
Figure 7. Buck2 Startup, VOUT2 = 1.8 V, IOUT2 = 5 mA
0.00010
0.15 0.14
0.00008
0.13 OUTPUT CURRENT (A) 0.12 0.11 0.10 0.09 0.08 0.07 PSM TO PWM PWM TO PSM
0.00006
IINA (A)
0.00004
0.00002
2.4
2.9
3.4 3.9 4.4 INPUT VOLTAGE (V)
4.9
5.4
Figure 5. System Quiescent Current vs. Input Voltage, VOUT1 = 0.8 V, VOUT2 = 2.5 V, VIN3 = VOUT2, VOUT3 = 1.2 V, All Channels Unloaded
Figure 8. Buck 2 PSM to PWM Transition, VOUT2 = 1.8 V
T 3.354 SW
4 2
TA = +25C TA = -40C TA = +85C
3.334 VOUT
VOUTA (V)
3.314
EN
1
3.294
IIN
3.274
3
3.254
CH1 2.00V CH3 5.00V
BW BW
CH2 50.0mA BW M 40.0s BW CH4 5.00V T 11.20%
A CH3
2.2V
08253-021
0
0.1
0.2
0.3 IOUT (A)
0.4
0.5
0.6
Figure 6. Buck1 Startup, VOUT1 = 3.3 V, IOUT1 = 10 mA
Figure 9. Buck1 Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode
Rev. A | Page 8 of 28
08253-058
3.234
08253-067
0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 VIN (V)
08253-064
0.06
08253-020
08253-023
ADP5022
1.834 1.824 1.814
EFFICIENCY (%)
100 TA = +25C TA = -40C TA = +85C 90 80 70 60 50 40 30 20 VIN = 3.6V VIN = 4.5V VIN = 5.5V
VOUTB (V)
1.804 1.794 1.784 1.774 1.764 0 0.1 0.2 0.3 IOUT (A) 0.4 0.5 0.6
10
08253-057
08253-038 08253-036 08253-039
0 0.0001
0.001
0.01 IOUT (A)
0.1
1
Figure 10. Buck2 Load Regulation Across Temperature, VOUT2 = 1.8 V, Auto Mode
Figure 13. Buck1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode
1.834 1.824 1.814
EFFICIENCY (%)
100 VIN = 5.5V VIN = 4.5V VIN = 3.6V VIN = 2.4V 90 80 70 60 50 40 30 20 VIN = 3.6V VIN = 4.5V VIN = 5.5V
VOUTB (V)
1.804 1.794 1.784
1.774 1.764 0 0.1 0.2 0.3 IOUT (A) 0.4 0.5 0.6
10
08253-054
0 0.001
0.01 IOUT (A)
0.1
1
Figure 11. Buck 2 Load Regulation Across Input Voltage, VOUT1 = 1.8 V, PWM Mode
Figure 14. Buck1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode
100 3.354 90 80 70
3.334
EFFICIENCY (%)
VOUTA (V)
3.314
60 50 40 30
3.294
3.274 VIN = 3.6V VIN = 4.5V VIN = 5.5V
08253-055
20 10 0.6 0 0.0001
3.254
VIN = 5.5V VIN = 4.5V VIN = 3.6V VIN = 2.4V 0.001 0.01 IOUT (A) 0.1 1
3.234 0 0.1 0.2 0.3 IOUT (A) 0.4 0.5
Figure 12. Buck1 Load Regulation Across Input Voltage, VOUT2 = 3.3 V, PWM Mode
Figure 15. Buck2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, Auto Mode
Rev. A | Page 9 of 28
ADP5022
100 90 80 70
EFFICIENCY (%)
100 90 80 70
EFFICIENCY (%)
60 50 40 30 20 10 0 0.001 VIN = 5.5V VIN = 4.5V VIN = 3.6V VIN = 2.4V
08253-035
60 50 40 30 20 10 0 0.0001 TA = -40C TA = +25C TA = +85C
08253-062
08253-040
0.01 IOUT (A)
0.1
1
0.001
0.01 IOUT (A)
0.1
1
Figure 16. Buck2 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode
100 90 80 70
EFFICIENCY (%)
Figure 19. Buck1 Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V, Auto Mode
100 90 80 70
EFFICIENCY (%)
60 50 40 30 20 10 0 0.0001 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V
08253-034
60 50 40 30 20 10 0 0.0001 TA = +25C TA = -40C TA = +85C
08253-063
0.001
0.01 IOUT (A)
0.1
1
0.001
0.01 IOUT (A)
0.1
1
Figure 17. Buck1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, Auto Mode
Figure 20. Buck2 Efficiency vs. Load Current, Across Temperature, VOUT2 = 1.8 V, Auto Mode
100 90 80 70 60 50 40 30 20 10 0 0.001 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V
08253-065
3.5 3.4 3.3
FREQUENCY (MHz)
TA = +25C TA = -40C TA = +85C
3.2 3.1 3.0 2.9 2.8 2.7 2.6
EFFICIENCY (%)
0.01 IOUT (A)
0.1
1
2.5 0 0.1 0.2 0.3 0.4 OUTPUT CURRENT (A) 0.5 0.6
Figure 18. Buck1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 0.8 V, PWM Mode
Figure 21. Buck2 Switching Frequency vs. Output Current, Across Temperature, VOUT2 = 1.8 V, PWM Mode
Rev. A | Page 10 of 28
ADP5022
T VOUT VOUT
1 1
T
ISW
2 2
ISW
SW
SW
4
4
CH1 50.0V
BW
CH2 500mA M 4.00s A CH2 BW CH4 2.00V T 28.40%
240mA
CH1 50mV
BW
CH2 500mA M 400ns A CH2 BW CH4 2.00V T 28.40%
08253-025
220mA
Figure 22. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
Figure 25. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode
T VOUT
1
T
VIN
ISW
2 1
VOUT SW
SW
3 4
CH1 50.0V
BW
CH2 500mA M 4.00s A CH2 BW CH4 2.00V T 28.40%
08253-024
220mA
CH1 50.0mV CH3 1.00V
BW BW
M 1.00ms CH4 2.00V
BW
A CH3
4.80V
T 30.40%
Figure 23. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Auto Mode
Figure 26. Buck1 Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode
T
T
VOUT
1
VIN ISW VOUT
2
1
SW
SW
4 3 4
CH1 50mV
BW
220mA
CH1 50.0mV CH3 1.00V
BW BW
M 1.00ms CH4 2.00V
BW
A CH3
4.80V
T 30.40%
Figure 24. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode
Figure 27. Buck2 Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode
Rev. A | Page 11 of 28
08253-013
CH2 500mA M 400ns A CH2 BW CH4 2.00V T 28.40%
08253-027
08253-012
08253-026
ADP5022
T
T SW
4
SW
4
VOUT
VOUT
1
1
IOUT
IOUT
2
08253-016
2
CH1 100mV
CH1 50.0mV
BW
CH2 50.0mA BW M 20.0s A CH2 BW T 60.000s CH4 5.00V
BW
BW BW
M 20.0s A CH2 T 19.20%
88.0mA
356mA
Figure 28. Buck1 Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Auto Mode
Figure 31. Buck2 Response to Load Transient, IOUT2 from 20 mA to 180 mA, VOUT2 = 1.8 V, Auto Mode
T SW
4 2
T VOUT2
SW1 VOUT
1 3
VOUT1
1
SW2
IOUT
2 4
CH1 50.0mV
BW
CH2 50.0mA BW M 20.0s A CH2 BW CH4 5.00V T 22.20%
08253-015
379mA
CH1 5.00V CH3 5.00V
BW BW
CH2 5.00V CH4 5.00V
BW BW
M 400ns T 50.00%
A CH4
1.90V
Figure 29. Buck2 Response to Load Transient, IOUT2 from 1 mA to 50 mA, VOUT2 = 1.8 V, Auto Mode
Figure 32. VOUT and SW Waveforms for Buck1 and Buck2 in PWM Mode Showing Out-of-Phase Operation
T SW
T
4 2
IIN
VOUT
1
VOUT
1
IOUT
EN
2
3
CH1 50.0mV
BW
BW BW
M 20.0s A CH2 T 20.40%
408mA
CH1 2.00V CH3 5.00V
BW BW
BW BW
M 40.0s T 11.20%
A CH3
2.2V
Figure 30. Buck1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, VOUT1 = 3.3 V, Auto Mode
Figure 33. LDO Startup, VOUT3 = 3.0 V, IOUT3 = 5 mA
Rev. A | Page 12 of 28
08253-022
CH2 200mA CH4 5.00V
08253-017
CH2 50.0mA
08253-066
08253-018
CH2 200mA CH4 5.00V
ADP5022
2.820 2.815 2.810
50 45 40
GROUND CURRENT (A)
35 30 25 20 15 10 5 150mA 100mA 10mA 1mA 100A 1A 3.8 4.3 4.8 INPUT VOLTAGE (V) 5.3
08253-043 08253-044 08253-030
2.805 VOUTC (V) 2.800 2.795 2.790 2.785 2.780 0 0.02 0.04 0.06 0.08 IOUT (A) 0.10 0.12 0.14 VIN = 3.3V VIN = 4.5V VIN = 5.0V VIN = 5.5V
08253-046
0 3.3
Figure 34. LDO Load Regulation Across Input Voltage, VOUT3 = 2.8 V
Figure 37. LDO Ground Current vs. Input Voltage, Across Output Load, VOUT3 = 2.8 V
2.85 2.84 2.83 2.82 TA = -40C TA = +25C TA = +85C
50 45 40 GROUND CURRENT (A)
0 0.02 0.04 0.06 0.08 0.10 IOUT (A) 0.12 0.14 0.16
08253-049
35 30 25 20 15 10 5 0 0 0.02 0.04 0.06 0.08 0.10 LOAD CURRENT (A) 0.12 0.14
VOUTC (V)
2.81 2.80 2.79 2.78 2.77 2.76 2.75
Figure 35. LDO Load Regulation Across Temperature, VIN3 = 3.3 V, VOUT3 = 2.8 V
Figure 38. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
3.0
3.0
2.5
2.5
2.0
2.0
VOUTC (V)
VOUTA (V)
IOUT = 150mA IOUT = 100mA IOUT = 10mA IOUT = 1mA IOUT = 100A
1.5
1.5
1.0
1.0 VIN = 3.6V VIN = 4.5V VIN = 5.5V
0.5
0.5
0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 VIN (V)
08253-045
0 0 0.05 0.10 0.15 0.20 0.25 IOUT (A) 0.30 0.35 0.40
Figure 36. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V
Figure 39. LDO Current Capability Across Input Voltage, VOUT3 = 2.8 V
Rev. A | Page 13 of 28
ADP5022
T
65 60 5VIN 3.3VIN
IOUT
55
2
RMS NOISE (V)
50 45 40 35 30
1
VOUT
CH1 100mV
BW
BW
M 40.0s A CH2 T 19.20%
52.0mA
08253-019
CH2 100mA
0.01
0.1
1 ILOAD (mA)
10
100
Figure 40. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA, VOUT3 = 2.8 V
Figure 43. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 3.0 V
0 -10 -20 100A 1mA 10mA 50mA 100mA 150mA
T
VIN
-30
PSRR (dB)
-40 -50 -60 -70 -80
VOUT
1 2
3
-90
08253-014
CH1 20.0mV CH3 1.00V
BW BW
M 100s T 28.40%
A CH3
4.80V
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 41. LDO Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT3 = 2.8 V
Figure 44. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
60 5VIN 55 3.3VIN 50
0
-20
RMS NOISE (V)
-40
PSRR (dB)
45
-60
40 35 30
-80 100A 1mA 10mA 50mA 100mA 150mA 100 1k 10k 100k FREQUENCY (Hz) 1M 10M
08253-051
-100
08253-047
25 0.001
0.01
0.1
1 ILOAD (mA)
10
100
-120 10
Figure 42. LDO Output Noise vs. Load Current, Across Input Voltage, VOUT3 = 2.8 V
Figure 45. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V
Rev. A | Page 14 of 28
08253-050
-100 10
08253-048
25 0.001
ADP5022
0 100A 1mA 10mA 50mA 100mA 150mA 0 -10 -20 -30 100A 1mA 10mA 50mA 100mA 150mA
-20
-40
PSRR (dB)
PSRR (dB)
08253-053
-40 -50 -60 -70 -80
-60
-80
-100 -90
08253-052
-120 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
-100 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 46. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V
Figure 47. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V
Rev. A | Page 15 of 28
ADP5022 THEORY OF OPERATION
VOUT1 GM ERROR AMP PWM COMP VIN1 ILIMIT PSM COMP PWM/ PSM CONTROL BUCK1 PSM COMP PWM/ PSM CONTROL BUCK2 SOFT START SOFT START ILIMIT VOUT2 GM ERROR AMP PWM COMP VIN2
LOW CURRENT SW1
LOW CURRENT SW2
OSCILLATOR DRIVER AND ANTISHOOT THROUGH PGND1 SYSTEM UNDERVOLTAGE LOCK OUT THERMAL SHUTDOWN DRIVER AND ANTISHOOT THROUGH PGND2
LDO UNDERVOLTAGE LOCK OUT EN1 EN2 EN3 ENABLE CONTROL LDO CONTROL R1
ADP5022
R2
08253-003
VDDA VIN3
AGND
VOUT3
MODE
Figure 48. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5022 is a micro power management units (micro PMU) combining two step-down (buck) dc-to-dc converters and a single low dropout linear regulator (LDO). The high switching frequency and tiny 16-ball WLCSP package allow for a small power management solution. To combine these high performance converters and regulators into the micro PMU, there is a system controller allowing them to operate together. Each regulator has a dedicated enable pin. EN1 controls the activation for Buck1, EN2 controls the activation for Buck2, and EN3 controls the activation of the LDO. Logic high applied to the ENx pin turns on the regulator, and a logic low applied to the ENx pin turns off the regulator. When a regulator is turned on, the output voltage is controlled through a soft start circuit to avoid a large inrush current due to the discharged output capacitors.
The buck regulators can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the switching frequency of the two bucks is always constant and does not change with the load current. If the MODE pin is at a logic low level, the switching regulators operate in an auto PWM/ PSM mode. In this mode, the regulators operate at fixed PWM frequency when the load current is above the power saving current threshold. When the load current falls below the power saving current threshold, the regulator in question enters power saving mode where the switching occurs in bursts. The burst repetition is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. The auto PWM/PSM mode transition is controlled independently for each buck regulator. The two bucks operate synchronized to each other.
Rev. A | Page 16 of 28
ADP5022
Thermal Protection
In the event that the junction temperature rises above 150C, the thermal shutdown circuit turns off the converters and the LDO. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20C hysteresis is included so that when thermal shutdown occurs, the bucks and LDO do not return to operation until the on-chip temperature drops below 130C. When coming out of thermal shutdown, soft start is initiated.
PWM Mode
In PWM mode, the bucks operate at a fixed frequency of 3 MHz set by an internal oscillator. At the start of each oscillator cycle, the PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFET switch and turns on the NFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the system. If the input voltage on VDDA drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channels, both the power switch and the synchronous rectifier turn off. When the voltage on VDDA rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for USB applications. For these models, the device hits the turn-off threshold when the input supply drops to 3.65 V typical.
Power Save Mode (PSM)
The bucks smoothly transition to PSM operation when the load current decreases below the PSM current threshold. When either of the bucks enter power save mode, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold.
Enable/Shutdown
When all three enable pins are held low, the device is in shutdown mode, and the input current remains below 2 A.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The bucks employ a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from the PSM. The PSM current threshold is optimized for excellent efficiency over all load currents.
BUCK SECTION
The two bucks use a fixed frequency and high speed current mode architecture. The bucks operate with an input voltage of 2.4 V to 5.5 V.
Control Scheme
The bucks operate with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency but shift to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency.
Oscillator/Phasing of Inductor Switching
The ADP5022 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Additionally, the ADP5022 ensures that when both bucks are in PWM mode, they operate out-of-phase, whereby the Buck2 PFET starts conducting exactly half a clock period after the Buck1 PFET starts conducting.
Rev. A | Page 17 of 28
ADP5022
Enable/Shutdown
The bucks start operation with soft start when the EN1 or EN2 pin is toggled from logic low to logic high. Pulling the EN1 or EN2 pin low disables that channel.
LDO SECTION
The LDO is a low quiescent current, low dropout linear regulator and provides up to 150 mA of output current. Drawing a low 30 A quiescent current (typical) at full load makes the LDO ideal for battery-operated portable equipment. The LDO operates with an input voltage of 2.3 V to 5.5 V. It also provides high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with just a small 1 F ceramic input and output capacitor. Internally, the LDO consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, reducing the current flowing to the output.
Short-Circuit Protection
The bucks include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current.
Soft Start
The bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter.
Current Limit
Each buck has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load.
LDO Undervoltage Lockout
The ADP5022 integrates an undervoltage lockout function on the VIN3 input voltage, which ensures that the LDO output drive is disabled whenever VIN3 is below a threshold of approximately 2.0 V. Where the ADP5022 is configured to supply VIN3 from either VOUT1 or VOUT2, this ensures that the LDO powers up safely in this cascaded configuration.
100% Duty Operation
With a drop in input voltage or with an increase in load current, the buck may reach a limit where, even with the PFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. Maintaining regulation is dependent on the input voltage, load current, and output voltage. This can be calculated from the following equation: VIN(MIN) = VOUT(MAX) + ILOAD(MAX) x (RDS(on)MAX + RL) where: VOUT(MAX) is the nominal output voltage plus the maximum tolerance. ILOAD(MAX) is the maximum load current plus inductor ripple current. RDS(on)MAX is the maximum P-channel switch RDS(on). RL is the DC resistance of the inductor.
Rev. A | Page 18 of 28
ADP5022 APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 1.
Output Capacitor
Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT x (1 - TEMPCO) x (1 - TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.2481 F at 1.8 V, as shown in Figure 49. Substituting these values in the equation yields CEFF = 9.2481 F x (1 - 0.15) x (1 - 0.1) = 7.0747 F To guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
12
Inductor
The high switching frequency of the ADP5022 bucks allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 H and 3 H. Suggested inductors are shown in Table 7. The peak-to-peak inductor current ripple is calculated using the following equation:
I RIPPLE =
VOUT x (VIN - VOUT ) VIN x f SW x L
where: fSW is the switching frequency. L is the inductor value. The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation:
I PEAK = I LOAD( MAX ) +
I RIPPLE 2
Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI.
Table 7. Suggested 1.0 H Inductors
Vendor Murata Murata Taiyo Yuden Coilcraft TDK Coilcraft Toko Model LQM2MPN1R0NG0B LQM18FN1R0M00B CBMF1608T1R0M EPL2014-102ML GLFR1608T1R0M-LR 0603LS-102 MDT2520-CN Dimensions (mm) 2.0 x 1.6 x 0.9 1.6 x 0.8 x 0.8 1.6 x 0.8 x 0.8 2.0 x 2.0 x 1.4 1.6 x 0.8 x 0.8 1.8 x 1.69 x 1.1 2.5 x 2.0 x 1.2 ISAT (mA) 1400 150 290 900 230 400 1350 DCR (m) 85 26 90 59 80 81 85
10
CAPACITANCE (F)
8
6
4
2
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
Figure 49. Typical Capacitor Performance
Rev. A | Page 19 of 28
08253-004
0
ADP5022
The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation:
VRIPPLE = I RIPPLE V IN = (2 x f SW ) x 2 x L x C OUT 8 x f SW x C OUT
Input Capacitor
Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation:
I CIN I LOAD ( MAX ) VOUT (VIN - VOUT ) VIN
Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation:
ESRCOUT VRIPPLE I RIPPLE
To minimize supply noise, place the input capacitor as close to the VIN pin of the BUCK as possible. As with the output capacitor, a low ESR capacitor is recommended. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 F and a maximum of 10 F. A list of suggested capacitors is shown in Table 9.
Table 9. Suggested 4.7 F Capacitors
The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 F and a maximum of 40 F.
Table 8. Suggested 10 F Capacitors
Vendor Murata Taiyo Yuden TDK Panasonic Type X5R X5R X5R X5R Model GRM188R60J106 JMK107BJ475 C1608JB0J106K ECJ1VB0J106M Case Size 0603 0603 0603 0603 Voltage Rating (V) 6.3 6.3 6.3 6.3
Vendor Murata Taiyo Yuden Panasonic
Type X5R X5R X5R
Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M
Case Size 0402 0402 0402
Voltage Rating (V) 6.3 6.3 6.3
The buck regulators require 10 F output capacitors to guarantee stability and response to rapid load variations and to transition in and out the PWM/PSM modes. In certain applications, where one or both buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 F to 4.7 F because the regulator does not expect a large load variation when working in PSM mode, see Figure 50.
ADP5022 L1 1H C2 MICRO PMU SW1 VIN1 4.7F VOUT1 VIN2 PGND1 C3 4.7F
VDDA MODE L2 1H VIO C5 4.7F ANALOG SUB-SYSTEM VANA
08253-005
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5022 LDO is designed for operation with small, spacesaving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP5022. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5022 to large changes in load current.
PROCESSOR VCORE C4 4.7F
VIN 2.5V TO 5.5V
Input Bypass Capacitor
GPIO
ALWAYS ON
VIN3 C1 1F SW2
VOUT2 PGND2 EN1 VOUT3 EN2 EN3
Connecting a 1 F capacitor from VIN3 to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance are encountered. If greater than 1 F of output capacitance is required, increase the input capacitor to match it.
Table 10. Suggested 1.0 F Capacitors
Vendor Murata TDK Panasonic Taiyo Yuden Type X5R X5R X5R X5R Model GRM155B30J105K C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F Case Size 0402 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3 10.0
ACTIVATION INPUTS
C6 1F
Figure 50. Processor System Power Management with PSM/PWM Control
Rev. A | Page 20 of 28
ADP5022
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5022 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 51 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating.
1.2
Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10% and CBIAS is 0.94 F at 1.8 V as shown in Figure 51. Substituting these values into the following equation. CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5022, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application.
1.0
CAPACITANCE (F)
0.8
0.6
0.4
0.2
0
1
2 3 4 DC BIAS VOLTAGE (V)
5
6
Figure 51. Capacitance vs. Voltage Characteristic
08253-006
0
Rev. A | Page 21 of 28
ADP5022 PCB LAYOUT GUIDELINES
Poor layout can affect ADP5022 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines:
* * * *
Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas.
Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
Rev. A | Page 22 of 28
ADP5022 EVALUATION BOARD SCHEMATICS AND ARTWORK
J1 J2 J3 J4 C3 0603 4.7F C1 0402 1F R1 0 J5 C2 0603 4.7F B1 B4 A4 A3 A2 C3 B2 B3 C2 R2 0 VIN1 VIN2 VDDA VIN3 AGND MODE EN1 EN2 EN3 LDO BUCK2 SW2 VOUT2 PGND2 VOUT3 C4 D3 D4 A1 COUT_3 0402 1F L2 1H COUT_2 0603 10F J10 BUCK1 SW1 VOUT1 PGND1 C1 D2 D1 L1 1H COUT_1 0603 10F
J8
J9
J13 J12
J7 J6
Figure 52. Evaluation Board Schematic
SUGGESTED LAYOUT
Figure 53. Top Layer, Recommended Layout
Figure 54. Second Layer, Recommended Layout
Rev. A | Page 23 of 28
08253-009
08253-008
08253-007
J11
ADP5022
Figure 55. Third Layer, Recommended Layout
Figure 56. Bottom Layer, Recommended Layout
Rev. A | Page 24 of 28
08253-011
08253-010
ADP5022 OUTLINE DIMENSIONS
2.12 2.08 SQ 2.04 0.660 0.602 0.544 0.022 REF SEATING PLANE
4 3 2 1 A
BALL 1 IDENTIFIER 0.330 0.310 0.290 1.50 REF
B
C
D
0.50 REF TOP VIEW
(BALL SIDE DOWN)
0.380 0.352 0.324
0.04 NOM COPLANARITY 0.280 0.250 0.220
BOTTOM VIEW
(BALL SIDE UP)
013009-B
Figure 57. 16-Ball Wafer Level Chip Scale Package [WLCSP] Back-Coating Included (CB-16-7) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP5022ACBZ-1-R72 Output Voltage (V)1 VOUT1 = 3.3 V VOUT2 = 1.5 V VOUT3 = 1.8 V VOUT1 = 1.2 V VOUT2 = 1.8 V VOUT3 = 2.8 V VOUT1 = 3.3 V VOUT2 = 1.8 V VOUT3 = 3.3 V Undervoltage Lockout Level Low Temperature Range -40C to +125C Package Description 16-Ball Wafer Level Chip Scale Package [WLCSP] Package Option CB-16-7 Branding Code L9H
ADP5022ACBZ-2-R72
Low
-40C to +125C
16-Ball Wafer Level Chip Scale Package [WLCSP]
CB-16-7
L9J
ADP5022ACBZ-4-R72
High
-40C to +125C
16-Ball Wafer Level Chip Scale Package [WLCSP]
CB-16-7
LG7
1
For additional voltage options, contact a local sales or distribution representative. Additional output voltages and UVLO available are
Buck1 and Buck2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.82 V, 1.8 V, 1.6 V, 1.5 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V LDO: 3.3 V, 3.0 V, 2.9 V, 2.8 V, 2.775 V, 2.5 V, 2.0 V, 1.875 V, 1.8 V, 1.75 V, 1.7 V, 1.65 V, 1.6 V, 1.55 V, 1.5 V, 1.2 V UVLO: 2.25 V or 3.9 V 2 Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
ADP5022 NOTES
Rev. A | Page 26 of 28
ADP5022 NOTES
Rev. A | Page 27 of 28
ADP5022 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08253-0-11/09(A)
Rev. A | Page 28 of 28

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